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ESMT
Mobile SDRAM
M52D128168A
Operation Temperature Condition -40C~85C
2M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
1.8V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) EMRS cycle with address All inputs are sampled at the positive going edge of the system clock Special function support - PASR (Partial Array Self Refresh) - TCSR (Temperature Compensated Self Refresh) - DS (Driver Strength) DQM for masking Auto & self refresh 64ms refresh period (4K cycle)
ORDERING INFORMATION
MAX FREQ. 133MHz 133MHz 100MHz 100MHz
PRODUCT NO. M52D128168A-7.5TIG M52D128168A-7.5BIG M52D128168A-10TIG M52D128168A-10BIG
PACKAGE 54 TSOP II 54 Ball FBGA 54 TSOP II 54 Ball FBGA
Comments Pb-free Pb-free Pb-free Pb-free
GENERAL DESCRIPTION
The M52D128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT (Top View)
1 2 DQ15 3 VSSQ 4 5 6 7 VDDQ 8 DQ0 9 VDD
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
A
VSS
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
NC
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
54 Ball FBGA (8x8mm) (mm ball pitch)
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Publication Date: Sep. 2008 Revision: 1.0 1/47
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FUNCTIONAL BLOCK DIAGRAM
CLK CKE
Clock Generator
M52D128168A
Operation Temperature Condition -40C~85C
Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter
Address
Mode Register
Bank A
Sense Amplifier Command Decoder Control Logic
CS RAS CAS WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Refresh Counter
L(U)DQM
Column Decoder
DQ
PIN FUNCTION DESCRIPTION
PIN CLK CS CKE A0 ~ A11 BA0 , BA1 NAME System Clock Chip Select Clock Enable Address Bank Select Address INPUT FUNCTION Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby. Row / column address are multiplexed on the same pins. Row address : RA0~RA11, column address : CA0~CA8 Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS Row Address Strobe RAS low. Enables row access & precharge. Latches column address on the positive going edge of the CLK with CAS Column Address Strobe CAS low. Enables column access. Enables write operation and row precharge.
WE
Write Enable Data Input / Output Mask Data Input / Output Power Supply / Ground Data Output Power / Ground No Connection
Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
L(U)DQM DQ0 ~ DQ15 VDD / VSS VDDQ / VSSQ NC
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Note: SYMBOL VIN, VOUT VDD, VDDQ TSTG PD IOS
M52D128168A
Operation Temperature Condition -40C~85C
VALUE -1.0 ~ 2.6 -1.0 ~ 2.6 -55 ~ +150 1 50
UNIT V V
C
W mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -40 to 85 C ) PARAMETER Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Note: SYMBOL VDD, VDDQ VIH VIL VOH VOL IIL IOL MIN 1.7 0.8xVDDQ -0.3 VDDQ-0.2 -2 -2 TYP 1.8 1.8 0 MAX 1.9 VDDQ+0.3 0.3 0.2 2 2 UNIT V V V V V 1 2 IOH = -0.1mA IOL = 0.1mA 3 4 NOTE
A A
1. VIH(max) = 2.2V AC for pulse width 3ns acceptable. 2. VIL(min) = -1.0V AC for pulse width 3ns acceptable. 3. Any input 0V VIN VDDQ, all other pins are not under test = 0V. 4. Dout is disabled , 0V VOUT VDDQ.
CAPACITANCE (VDD = 1.8V, TA = 25 C , f = 1MHZ)
PARAMETER Input capacitance (A0 ~ A11, BA0 ~ BA1) Input capacitance (CLK, CKE, CS , RAS , CAS , WE & L(U)DQM) Data input/output capacitance (DQ0 ~ DQ15) CIN2 1.5 3.5 pF SYMBOL CIN1 MIN 1.5 MAX 3.0 UNIT pF
COUT
2.0
4.5
pF
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DC CHARACTERISTICS
Recommended operating condition unless otherwise notedTA = -40 to 85 C Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N Test Condition
M52D128168A
Operation Temperature Condition -40C~85C
CAS Latency
Version -7.5 65 0.5 0.5 10 -10 65
Unit Note mA mA mA mA 1
Burst Length = 1 tRC tRC (min), tCC tCC (min), IOL= 0mA CKE VIL(max), tCC =15ns CKE VIL(max), CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC =10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC =15ns CKE VIL(max), CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC=15ns Input signals are changed one time during 2clks All other pins VDD-0.2V or 0.2V CKE VIH (min), CLK VIL(max), tCC= Input signals are stable IOL= 0mA, Page Burst All Band Activated, tCCD = tCCD (min) tRC tRC(min) TCSR range
ICC2NS Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) ICC3P ICC3PS ICC3N
10 5 2 25
mA mA
mA
ICC3NS Operating Current (Burst Mode) Refresh Current
15 75 120 15 380 360 340 45 400 380 350 10 70 100 70 450 450 350
mA mA 1
ICC4 ICC5
uA C uA
2
Self Refresh Current
ICC6
CKE 0.2V
4 Banks 2 Bank 1 Bank
Deep Power Down Current
ICC7
CKE 0.2V
uA
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min). 2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).
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AC OPERATING TEST CONDITIONS (VDD=1.8V 0.1V,TA= -40 C ~ 85 C ) Parameter Value Input levels (Vih/Vil) 0.9 x VDDQ / 0.2 Input timing measurement reference level 0.5 x VDDQ Input rise and fall time tr / tf = 1 / 1 Output timing measurement reference level 0.5 x VDDQ Output load condition See Fig.2
1.8V
M52D128168A
Operation Temperature Condition -40C~85C
Unit V V ns V
Vtt =0.5x VDDQ
13.9K 50 Output VOH(DC) = VDDQ-0.2V, IOH = -0.1mA VOL(DC) = 0.2V, IOL = 0.1mA Output Z0=50 20 pF
10.6K
20 pF
(Fig.1) DC Output Load circuit
(Fig.2) AC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time @Operating @Auto refresh Last data in to new col. Address delay Last data in to row precharge Last data in to burst stop Col. Address to col. Address delay
Mode Register command to Active or Refresh Command
Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max)
Version -7.5 15 15 15 48 100 67.5 80 1 2 1 1 2 2 1 64 90 -10 20 20 20 50
Unit ns ns ns ns us ns ns CLK CLK CLK CLK CLK ea ms
Note 1 1 1 1 1 1,5 2 2 2 3 4 6
Row cycle time
tRC(min) tRFC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) tMRD(min) CAS latency=3 CAS latency=2
Number of valid output data Refresh period(4,096 rows)
tREF(max)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 3. Minimum delay is required to complete write. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks 5. A new command may be given Trfc after self refresh exit. 6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM,and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6s.)
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M52D128168A
Operation Temperature Condition -40C~85C
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CLK cycle time CLK to valid output delay CAS Latency =3 CAS Latency =2 CAS Latency =3 CAS Latency =2
Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ
-7.5 Min 7.5 10 Max 1000 7 8 2.5 2.5 2.5 2.5 1 1 7 8 2.5 3 3 2.5 1.5 1 Min 10 12
-10 Max 1000 9 10
Unit ns ns ns ns ns ns ns ns
Note 1 1 2 3 3 3 3 2
Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS Latency =3 CAS Latency =2
9 10
ns
*All AC parameters are measured from half to half. Note: 1.Parameters depend on programmed CAS latency. 2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter.
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SIMPLIFIED TRUTH TABLE
COMMAND Mode Register set Register Extended Mode Register set Auto Refresh Refresh Self Refresh Entry Exit Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable H Auto Precharge Enable Auto Precharge Disable H Auto Precharge Enable H H All Banks H Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operating Command L H H H X L H L V X X H X H V H L H L L H L L H H X H X X H V X X V X X X X X X L L H L H H L L X L H L L X L H L H H X H L H X L L L H H L L H X L L H X H L L L L CKEn-1 CKEn CS RAS CAS
M52D128168A
Operation Temperature Condition -40C~85C
WE
DQM BA0 A10/AP BA1 X
A11 A9~A0
Note
OP CODE
1,2 3
H H X H H
X X X X X V V H L X X V X X H L V H
X
3 3
X Row Address L Column Address (A0~A8) Column Address (A0~A8) X X
3
4 4,5 4 4,5 6
Burst Stop Bank Selection Precharge
X X V X X X H X X V V X H X X X 7 X X X
(V = Valid , X = Don't Care. H = Logic High , L = Logic Low ) Note : 1.OP Code : Operating Code A0~A11 & BA0~BA1 : Program keys. (@ MRS). BA1=0 for MRS and BA1=1 for EMRS 2.MRS/EMRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS/EMRS. 3.Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge of command is meant by "Auto". Auto/self refresh can be issued only at all banks idle state. 4.BA0~BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read ,write , row active and precharge ,bank A is selected. If both BA0 is "Low" and BA1 is "High" at read ,write , row active and precharge ,bank B is selected. If both BA0 is "High" and BA1 is "Low" at read ,write , row active and precharge ,bank C is selected. If both BA0 and BA1 are "High" at read ,write , row active and precharge ,bank D is selected If A10/AP is "High" at row precharge , BA0 and BA1 is ignored and all banks are selected. 5.During burst read or write with auto precharge. new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6.Burst stop command is valid at every burst length. 7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
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makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
M52D128168A
Operation Temperature Condition -40C~85C
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS Address Function BA0 0 BA1 0 A11 0 A10/AP 0 A9 0 A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 A0
CAS Latency
Burst Length
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1
CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Burst Type A3 0 1 Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length : 512
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BA1 BA0 A11 A10 1 0 0 0 A9 0 A8 A7 0 0 A6 A5 A4 DS 0 A3 0 A2 A1 A0 PASR
M52D128168A
Operation Temperature Condition -40C~85C
Address bus Extended Mode Register Set A2-A0 000 001 PASR 010 011 100 101 111 Self Refresh Coverage 4Bank 2 Bank (BankA& BankB) or (BA1=0) 1 Bank (BankA) or (BA0=BA1=0) R R R R
DS
A6-A5 00 01 10 11
Driver Strength Full Strength 1/2 Strength 1/4 Strength R Remark R : Reserved
EXTENDED MODE REGISTER SET (EMRS) The extended mode register stores for selecting PASR; DS. The extended mode register set must be done before any active command after the power up sequence. The extended mode register is written by asserting low on CS,RAS,CAS,WE and high on BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more register). The state of address pins A0~An in the same cycle as CS,RAS,CAS,WE going low is written in the extended mode register. Refer to the table for specific codes. The extended mode register can be changed by using the same command and clock cycle requirements during operations as long as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks refreshed.
Internal Temperature Compensated Self Refresh (TCSR)
Note : 1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the three temperature range : 15C, 45C and 70C. 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. 3. It has +/-5C tolerance
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BURST SEQUENCE (BURST LENGTH = 4)
Initial Adrress A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 Sequential
M52D128168A
Operation Temperature Condition -40C~85C
Interleave
1 0 3 2
2 3 0 1
3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Sequential Interleave
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DEVICE OPERATIONS
CLOCK (CLK) The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and Icc specifications. CLOCK ENABLE(CKE) The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. BANK ADDRESSES (BA0~BA1) This SDRAM is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. The BA0~BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The banks addressed BA0~BA1 are latched at bank active, read, write, mode register set and precharge operations. ADDRESS INPUTS (A0~A11) The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (A0~A11). The 12 row addresses are latched along with RAS and BA0~BA1 during bank active command. The 9 bit column addresses are latched along with CAS , WE and BA0~BA1 during read or with command. NOP and DEVICE DESELECT When RAS , CAS and WE are high, The SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS , CAS , WE and all the address inputs are ignored.
M52D128168A
Operation Temperature Condition -40C~85C
MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS , RAS , CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11 and BA0~BA1 in the same cycle as CS , RAS , CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields into depending on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) use A4~A6, test mode use A7~A8, vendor specific options use A9, A10~A11 and BA1~BA0. A7~A8, A10/AP~A11 and BA0~BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
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DEVICE OPERATIONS (Continued)
BANK ACTIVATE The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD (min) from the time of bank activation. tRCD is the internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding of the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD (min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS (min). Every SDRAM bank activate command must satisfy tRAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max) and tRAS (max) can be calculated similar to tRCD specification. BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and RAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD (min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length
M52D128168A
Operation Temperature Condition -40C~85C
and burst sequence. By asserting low on CS , CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also. DQM OPERATION The DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram also. PRECHARGE The precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and CS , RAS , WE and A10/AP with valid BA0~BA1 of the bank to be procharged. The precharge command can be asserted anytime after tRAS (min) is satisfy from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS (max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state.
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DEVICE OPERATIONS (Continued)
AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS (min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. BOTH BANKS PRECHARGE A11 banks can be precharged at the same time by using Precharge all command. Asserting low on CS , RAS , and
WE with high on A10/AP after all banks have satisfied tRAS requirement, performs precharge on all banks. At the end of tRP after performing precharge all, all banks are in idle state.
(min)
M52D128168A
Operation Temperature Condition -40C~85C
SELF REFRESH The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS , RAS , CAS and CKE with high on WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation.
AUTO REFRESH The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS , RAS and CAS with high on CKE and WE . The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC (min). The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us.
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ESMT
COMMANDS Mode register set command
M52D128168A
Operation Temperature Condition -40C~85C
( CS , RAS , CAS , WE , BA1, BA0 = Low)
The DRAM has a mode register that defines how the device operates. In this command, A0 through BA0 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK (tMRD) following this command, the DRAM cannot accept any other commands.
Extended Mode register set command
( CS , RAS , CAS , WE , BA0 = Low ; BA1= High) The DRAM has a extended mode register that defines how to set PASR, DS.
Activate command
( CS , RAS = Low, CAS , WE = High) The DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA1 and BA0 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's RAS falling.
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Precharge command
( CS , RAS , WE = Low, CAS = High ) This command begins precharge operation of the bank selected by BA1 and BA0 (BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10 is Low, only the bank selected by BA1 and BA0 is precharged. After this command, the DRAM can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's RAS rising.
M52D128168A
Operation Temperature Condition -40C~85C
Write command
( CS , CAS , WE = Low, RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks.
Read command
( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address.
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ESMT
CBR (auto) refresh command
( CS , RAS , CAS = Low, WE , CKE = High)
M52D128168A
Operation Temperature Condition -40C~85C
This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the DRAM cannot accept any other command.
Self refresh entry command
( CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged.
Burst stop command
( CS , WE = Low, RAS , CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length.
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ESMT
No operation
( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command.
M52D128168A
Operation Temperature Condition -40C~85C
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ESMT
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1 ) Cl o c k S u sp e n d e d D u r in g W r i t e ( B L = 4 )
M52D128168A
Operation Temperature Condition -40C~85C
2 ) C lo c k S u s p e n d e d D u r i n g R e a d ( B L =4 )
CLK CM D WR RD
CK E I nt e r n al CL K DQ ( C L 2 ) DQ ( C L 3 ) D0 D1 D1
Masked by C KE
D2
D3
Q0
Q1
Q2
Q3
D0
D2
D3
Q0
Q1
Q2
Q3
N o t W r i tt e n
Su s pe nd ed D ou t
2. DQM Operation
1)W rite Mask (BL=4)
2) Read Mas k (B L= 4)
CLK CMD WR
RD
DQM
Ma s k e d b y D Q M Ma s k e d b y D Q M Hi- Z
DQ(CL2)
D0
D1
D3 D3
Q0
Q2 Q1
Q3
DQ(CL3)
Hi- Z
D0
D1
Q2
Q3
DQ M t o D at a -i n M ask = 0
DQ M to D at a- ou t M ask = 2
*Note2 3)DQM with clc ok su sp end ed (F ull Page Read )
CLK
CMD
RD
CKE Inter nal CLK DQM
Hi- Z Hi-Z Hi- Z
DQ(CL2)
Q0
Hi-Z
Q2
Hi-Z
Q4
Hi-Z
Q6
Q7
Q8
Q9
DQ(CL3)
Q1
Q3
Q5
Q6
Q7
Q8
*Note :1. CKE to CLK disable/enable = 1CLK. 2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE "L". 3. DQM masks both data-in and data-out.
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ESMT
3. CAS Interrupt (I)
M52D128168A
Operation Temperature Condition -40C~85C
* Not e 1 1) Re ad i nt e rr upt ed b y R ea d ( B L= 4)
CLK CMD RD A RD
ADD
B
D Q ( CL 2 ) DQ ( C L 3 )
Q A0
QB0 QA0
QB1 Q B0
QB2 QB1
QB3
QB2
QB3
tC C D
*N ote 2
2) W ri t e i n t e rr up t ed by W r it e ( B L = 2)
3 ) Wr it e i nt e rr u pt e d b y R e a d ( B L = 2)
CL K
CMD
WR
WR
* N ote 2
WR
RD
* No t e 2
tC CD
ADD DQ A
t CC D
A D Q ( CL 2 ) DQ ( C L 3 ) DA0
B
B DB 0 DB1
DA 0
DB0
DB 1
t CD L
*N ote 3
DA0
DB0
DB1
t CD L
*N ote 3
*Note : 1. By "interrupt" is meant to stop burst read/write by external before the end of burst. By " CAS interrupt ", to stop burst read/write by CAS access; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK)
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ESMT
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
M52D128168A
Operation Temperature Condition -40C~85C
( a) CL =2 ,B L= 4
CLK i)CMD
RD
WR
DQM
DQ
D0
D1
D2
D3
ii)CMD DQM
RD
WR
DQ
Hi-Z
D0
D1
D2
D3
iii)CMD
RD
WR
DQM Hi-Z
DQ
D0
D1
D2
D3
iv)CMD DQM
RD
WR
DQ
Q0
HH - ZZ i i*Note1
D0
D1
D2
D3
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ESMT
(b) CL =3 ,B L= 4 CLK i)CMD RD WR
M52D128168A
Operation Temperature Condition -40C~85C
DQM
DQ
D0
D1 WR
D2
D3
ii)CMD DQM
RD
DQ
D0
D1
D2
D3
iii)CMD DQM
RD
WR
DQ
D0
D1
D2
D3
iv)CMD DQM
RD
WR
DQ
Hi-Z
D0
D1
D2
D3
v)CM D
RD
WR
DQM Hi-Z Q0
*Note1
DQ
D0
D1
D2
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
CLK CMD
*Note3
WR
*Note2
DQM DQ
D0
D1
D2
D3
Ma s k e d b y D Q M
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation.
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ESMT
6. Precharge
M52D128168A
Operation Temperature Condition -40C~85C
1)Normal W rit e (BL=4)
2) Norm al R ead (B L= 4)
CLK CMD
CLK PRE CMD PRE CL=2
*Note2
WR
RD Q0 Q1
DQ
D0
D1
D2
D3
DQ(CL2)
Q2
Q3
tRD L
*Note1
CMD
PRE CL= 3
*Note2
DQ( CL3)
Q0
Q1
Q2
Q3
.
7. Auto Precharge
1)Normal W rit e (BL=4)
2) Normal Read (B L= 4)
CLK
CLK CMD
CMD DQ
WR
RD D0 D2 D3
D0
D1
D2
D3
DQ(CL2)
D1
tRDL
(min )
DQ(CL3)
*Note3
D0
D1
D2
D3
Aut o Pr ech ar ge st ar t s
*Note3
Auto Pr ech arge st art s
*Note : 1. tRDL : Last data in to row precharge delay. 2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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ESMT
8. Burst Stop & Interrupted by Precharge
1) W ri te B ur s t S t op ( BL= 8 )
M52D128168A
Operation Temperature Condition -40C~85C
1) W ri t e in t err up t ed by pr ec ha rg e ( B L= 4)
CLK CM D ST OP
CLK
*N ote3
WR
CM D
WR
PRE
t R DL
*N ote4
DQ M DQ
DQ M DQ Mask Mask
D0
D1
D2
D3
D4
D5
D0
D1
t B DL
*N ote1
2 )R e ad B ur s t S t op (B L= 4)
2 )R ea d i nt er ru pt ed by pr ec har ge (B L =4)
CL K CMD RD STO P
*N ote2
CL K CMD
*N ote5
RD
PRE
DQ ( C L 2 )
Q0
Q1
* Not e 2
D Q( C L3)
Q0
Q1
D Q( C L2)
Q0
Q1
Q2
Q3 Q3
D Q ( CL 3 )
Q0
Q1
Q2
9. MRS
1 )M o d e R e g is t e r S e t
CLK
*N o t e 6
CMD
PRE
M RS
ACT
t RP
2C LK
*Note:
1. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely. 3. Write burst is terminated. tRDL determinates the last data write. 4. DQM asserted to prevent corruption of locations D2 and D3. 5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM. 6. PRE : All banks precharge, if necessary. MRS can be issued only at all banks precharge state.
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ESMT
10. Clock Suspend Exit & Power Down Exit
M52D128168A
Operation Temperature Condition -40C~85C
1) Cl o ck S u sp en d (= Ac t ive P ow er Do wn ) Exi t
2)P ower Down (= Pr ec harg e Powe r Down )
CLK CKE Inter nal CLK CMD
CLK
tSS
*Note1
CKE Internal CLK RD CMD
tSS
*Note2
NOP AC T
11. Auto Refresh & Self Refresh
1) A u t o Re f r es h & S e lf R ef r e s h
*N ote3
CLK
*N ote4 * No t e 5
CM D
PRE
AR
CM D
CKE
t RP
2 ) S el f Re f r es h *N ote6
t RF C
CLK
*N ote4
CM D
PRE
SR
CMD
CKE
tRP
tR F C
*Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh entry, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh entry, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
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ESMT
12. About Burst Type Control
M52D128168A
Operation Temperature Condition -40C~85C
Sequential Counting Basic MODE Interleave Counting
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 1, 2, 4, 8 and full page. At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random MODE
Random Column Access tCCD = 1 CLK
13. About Burst Length Control
1 2 4 8 Full Page Random MODE Burst Stop RAS Interrupt (Interrupted by Precharge)
At MRS A210 = "000" At auto precharge . tRAS should not be violated. At MRS A210 = "001" At auto precharge . tRAS should not be violated. At MRS A210 = "010" At MRS A210 = "011" At MRS A210 = "111" At the end of the burst length , burst is warp-around. tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. Using burst stop command, any burst length control is possible. Before the end of burst. Row precharge command of the same bank stops read /write burst with auto precharge. tRDL = 2clk with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued.
Basic MODE
Interrupt MODE
CAS Interrupt
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ESMT
FUNCTION TURTH TABLE (TABLE 1) Current State CS RAS CAS
WE
M52D128168A
Operation Temperature Condition -40C~85C
BA
ADDR
ACTION
Note
IDLE
Row Active
Read
Write
Read with Auto Precharge
Write with Auto Precharge
H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L H L L L L L
X H H H L L L L X H H H H L L L X H H H H L L L X H H H H L L L X H H H L L X H H H L L
X H H L H H L L X H H L L H H L X H H L L H H L X H H L L H H L X H H L H L X H H L H L
X H L X H L H L X H L H L H L X X H L H L H L X X H L H L H L X X H L X X X X H L X X X
X X X BA BA BA X OP code X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA X X X X BA BA X
X X X CA, A10/AP RA A10/AP X OP code X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP RA, RA10 X X X X CA, A10/AP RA, RA10 X
NOP NOP ILLEGAL ILLEGAL Row (&Bank) Active ; Latch RA NOP Auto Refresh or Self Refresh Mode Register Access NOP NOP ILLEGAL Begin Read ; latch CA ; determine AP Begin Write ; latch CA ; determine AP ILLEGAL Precharge ILLEGAL NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) Term burst Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Reads ILLEGAL NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) Term burst Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Writes ILLEGAL NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) ILLEGAL ILLEGAL ILLEGAL ILLEGAL
2 2 4 5 5
2
2
3 2
3 3 2 3
2
2
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ESMT
Current State CS RAS CAS
WE
M52D128168A
Operation Temperature Condition -40C~85C
BA
ADDR
ACTION
Note
Precharging
Row Activating
Refreshing
Mode Register Accessing
H L L L L L L H L L L L L L H L L L L H L L L L
X H H H L L L X H H H L L L X H H L L X H H H L
X H H L H H L X H H L H H L X H L H L X H H L X
X H L X H L X X H L X H L X X X X X X X H L X X
X X X BA BA BA X X X X BA BA BA X X X X X X X X X X X
X X X CA RA A10/AP X X X X CA RA A10/AP X X X X X X X X X X X
NOP Idle after tRP NOP Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRP ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRFC NOP Idle after tRFC ILLEGAL ILLEGAL ILLEGAL NOP Idle after 2clocks NOP Idle after 2clocks ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address
2 2 2 4
2 2 2 2
Abbreviations :
RA = Row Address NOP = No Operation Command
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle.
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ESMT
FUNCTION TRUTH TABLE (TABLE2) Current State CKE ( n-1 ) H L L L L L L H L L L L L L H H H H H H H H H L H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L L H L H L CS RAS CAS
WE
M52D128168A
Operation Temperature Condition -40C~85C
ADDR
ACTION
Note
Self Refresh
All Banks Precharge Power Down
All Banks Idle
Any State other than Listed above
X H L L L L X X H L L L L X X H L L L L L L L X X X X X
X X H H H L X X X H H H L X X X H H H L L L L X X X X X
X X H H L X X X X H H L X X X X H H L H H L L X X X X X
X X H L X X X X X H L X X X X X H L X H H L L X X X X X
X X X X X X X X X X X X X X X X X X X RA X X OP Code X X X X X
INVALID Exit Self Refresh Idle after tRFC (ABI) Exit Self Refresh Idle after tRFC (ABI) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL Row (& Bank) Active NOP Enter Self Refresh Mode Register Access NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
6 6
7 7
8 8
8
9 9
Abbreviations : ABI = All Banks Idle, RA = Row Address
*Note : 6.CKE low to high transition is asynchronous. 7.CKE low to high transition is asynchronous if restart internal clock. A minimum setup time 1CLK + tSS must be satisfy before any command other than exit. 8.Power down and self refresh can be entered only from the all banks idle state. 9.Must be a legal command.
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ESMT
M52D128168A
Operation Temperature Condition -40C~85C
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3,Burst Length = 1
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ESMT
Note :
M52D128168A
Operation Temperature Condition -40C~85C
1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active @ read/write are controlled by BA0~BA1.
BA1 BA0 Active & Read/Write
0 0 1 1
0 1 0 1
Bank A Bank B Bank C Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP BA1 BA0 Operating
0 0 0 1 1 0 1 0 1 1
0 1 0 1 0 1 0 1
Disable auto precharge, leave A bank active at end of burst. Disable auto precharge, leave B bank active at end of burst. Disable auto precharge, leave C bank active at end of burst. Disable auto precharge, leave D bank active at end of burst. Enable auto precharge , precharge bank A at end of burst. Enable auto precharge , precharge bank B at end of burst. Enable auto precharge , precharge bank C at end of burst. Enable auto precharge , precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP BA1 BA0 Precharge
0 0 0 0 1
0 0 1 1 X
0 1 0 1 X
Bank A Bank B Bank C Bank D All Banks
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ESMT
Power Up Sequence
0
CLOCK
M52D128168A
Operation Temperature Condition -40C~85C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CKE
High level is necessary
CS
tRP
RAS
tRFC
tRFC
tMRD
tMRD
CAS
ADDR
Key
Key
RA
BA1
BS
BA0
BS
A10 /AP
RA
DQ
High-Z
WE
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Re fresh
Mode Register Set Row Active Extended Mode Register Set : Don't care
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) Apply VDD before or at the same time as VDDQ Apply VDDQ 2. Start clock and maintain stable condition for a minimum. 3. The minimum of 200us after stable power and clock (CLK,CLK),apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. 5. Issue 2 or more auto-refresh commands. 6. Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS..
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Read & Write Cycle at Same Bank @ Burst Length = 4
0
CLOCK
M52D128168A
Operation Temperature Condition -40C~85C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH CKE
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Ca0
Rb
Cb0
BA1
BA0
A10/AP
Ra
Rb
CL =2 DQ CL =3
Qa0
Qa1
Qa2
Qa3
*Not e3
Qb0
Qb1
Qb2
Qb3
tRDL
Qb0
*Note3
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
tRDL
WE
DQM
Row Active ( A - Bank )
Read ( A - Bank )
Precharge ( A - Bank )
Row Active ( A - Bank )
Write ( A - Bank )
Precharge (A - Bank)
:Don't Care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 32/47
ESMT
Page Read & Write Cycle at Same Bank @ Burst Length = 4
M52D128168A
Operation Temperature Condition -40C~85C
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 33/47
ESMT
Page Read Cycle at Different Bank @ Burst Length = 4
M52D128168A
Operation Temperature Condition -40C~85C
Note: 1. CS can be don't cared when RAS , CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 34/47
ESMT
Page Write Cycle at Different Bank @ Burst Length = 4
M52D128168A
Operation Temperature Condition -40C~85C
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 35/47
ESMT
Read & Write Cycle at Different Bank @ Burst Length = 4
M52D128168A
Operation Temperature Condition -40C~85C
*Note : 1. tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 36/47
ESMT
Read & Write cycle with Auto Precharge @ Burst Length = 4
M52D128168A
Operation Temperature Condition -40C~85C
*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 37/47
ESMT
M52D128168A
Operation Temperature Condition -40C~85C
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
*Note : 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 38/47
ESMT
M52D128168A
Operation Temperature Condition -40C~85C
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycles". 2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 39/47
ESMT
M52D128168A
Operation Temperature Condition -40C~85C
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 40/47
ESMT
M52D128168A
Operation Temperature Condition -40C~85C
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
*Note:
1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tSS prior to Row active command. 3. Can not violate minimum refresh specification. (64ms)
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 41/47
ESMT
Self Refresh Entry & Exit Cycle
M52D128168A
Operation Temperature Condition -40C~85C
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. Burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 42/47
ESMT
Mode Register Set Cycle
0 CLOCK 1 2 3 4 5 6 CLOCK 0 1
M52D128168A
Operation Temperature Condition -40C~85C
Extended Mode Register Set Cycle
2 3 4 5 6
CKE
HIGH
CKE
HIGH
CS
*Note2
CS
* Not e2
RAS
RAS
*Note1
* Note1
CAS
CAS
*Note3
* Note3
ADDR
Key
Ra
ADDR
Key
Ra
BA1
BS
BA1
BS
BA0
BS
BA0
BS
A10
A10
DQ
HI-Z
DQ
HI-Z
WE
WE
DQM
DQM
MRS
New Command
EMRS
New Command
:Don't Care
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 43/47
ESMT
M52D128168A
Operation Temperature Condition -40C~85C
PACKING DIMENSIONS 54-LEAD TSOP(II) SDRAM (400mil) (1:3)
-H-
D
54 28
SEE DETAIL A
A A2
0.21 REF 0.665 REF
B
A1
PIN1 IDENTIFIER
E1
E
-CB
O L L1
1
27
DETAIL "A"
-C-
b
-C-
c c1
0.10
e
SEATING PLANE
b
b1 SECTION B-B
Symbol A A1 A2 b b1 c c1 D E E1 L L1 e
Dimension in mm Min Norm Max 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.25 0.45 0.25 0.35 0.40 0.12 0.21 0.10 0.127 0.16 22.22 BSC 11.76 BSC 10.16 BSC 0.40 0.50 0.60 0.80 REF 0.80 BSC 0 10
Dimension in inch Min Norm Max 0.047 0.002 0.004 0.006 0.037 0.039 0.041 0.010 0.018 0.010 0.014 0.016 0.005 0.008 0.004 0.005 0.006 0.875 BSC 0.463 BSC 0.400 BSC 0.016 0.020 0.024 0.031 REF 0.031 BSC 0 10
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 44/47
ESMT
PACKING 54-BALL DIMENSIONS SDRAM ( 8x8 mm )
M52D128168A
Operation Temperature Condition -40C~85C
Dimension in mm Min Norm Max A 1.00 A1 0.20 0.25 0.30 A2 0.61 0.66 0.71 b 0.30 0.35 0.40 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D1 6.40 E1 6.40 e 0.80 Controlling dimension : Millimeter.
Symbol
Dimension in inch Min Norm Max 0.039 0.008 0.010 0.012 0.024 0.026 0.028 0.012 0.014 0.016 0.311 0.315 0.319 0.311 0.315 0.319 0.252 0.252 0.031
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 45/47
ESMT
Revision History
Revision Date
M52D128168A
Operation Temperature Condition -40C~85C
Description
1.0
2008.09.02
Original
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 46/47
ESMT
Important Notice All rights reserved.
M52D128168A
Operation Temperature Condition -40C~85C
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2008 Revision: 1.0 47/47

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